1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a technique for reducing the power consumption of a semiconductor integrated circuit to which a forward body bias is applied.
2. Description of the Background Art
Attempts have been made to improve the degree of integration and the operation speed of semiconductor integrated circuits by providing a large number of insulated-gate field effect transistors such as MOSFETs and MISFETs and by reducing the thickness of the gate oxide film while shortening the channel length by miniaturization processes. However, this leads to a decrease in the transistor threshold voltage and an increase in the proportion of the leak current to the power consumption. Moreover, the shortened gate length results in significant variations in characteristics of MOS transistors such as the threshold voltage. As a countermeasure, a DVS (Dynamic Voltage Scaling) technique is known in the art, which realizes a reduction in the power consumption of a semiconductor integrated circuit by suppressing the leak current by dynamically changing the voltage value of the voltage supplied from the power supply circuit according to the amount of processing to be done by a processor and a SOC (System On chip).
With CMOS devices, the characteristics can be improved to some extent by adjusting the source-substrate voltage, i.e., the body bias. Specifically, if a forward body bias (FBB) is applied to a CMOS device, the threshold voltage and the operating voltage of a MOS transistor decrease, thereby making various improvements such as a suppression in the characteristics variations, a decrease in the power consumption, an increase in the operating speed (see, for example, Non-Patent Document 1). With a FBB-controlled semiconductor integrated circuit, the area efficiency is improved by employing a layout in which a substrate potential supply cell including a metal line for supplying the body bias is sandwiched between logic cells (see, for example, Patent Document 1).
Another approach to realizing a lower power consumption is to use charge reusing circuits (so-called “charge recycling circuits”) to thereby increase the power conversion efficiency of a power supply circuit, e.g., a linear regulator circuit (see, for example, Patent Document 2).
Patent Document 1: Japanese Laid-Open Patent Publication No. 2001-148464
Patent Document 2: Japanese Patent No. 2774244
Non-Patent Document 1: M. Miyazaki, et al., “A 175 mV Multiply-Accumulate Unit using an Adaptive Supply Voltage and Body Bias (ASB) Architecture”, ISSCC 2002/SESSION 3/DIGITAL SIGNAL PROCESSORS AND CIRCUITS/3.4
However, as pointed out in Non-Patent Document 1, if the forward body bias applied to the CMOS device exceeds a certain level, the leak current rapidly increases and the power consumption increases while the frequency characteristics of the CMOS device deteriorate. This is because as the body bias increases, the current flowing through a forward diode, a parasitic bipolar, etc., formed by a P substrate, an N well, a P well, a source region diffusion layer, etc., will have a more significant influence on the CMOS device. Therefore, if an excessively large forward body bias is applied to the CMOS device, it will rather deteriorate the operating characteristics.
In recent years, the power consumption of a semiconductor integrated circuit is reduced by lowering the operating voltage of CMOS devices. However, if a very high forward body bias is applied to a CMOS device operating at a low voltage, the substrate voltage in the N well becomes lower than that in the P well, resulting in a forward current flow in the PN junction diode formed by these wells, whereby the substrate voltage of the P well will be lower than the actually applied body bias. Since there is a forward current in the PN junction diode formed by a P substrate and an N well, the substrate voltage in the N well will be higher than the actually applied body bias. Thus, with CMOS devices operating at low voltages, it is not possible to apply a very large forward body bias, and it is therefore difficult to improve the characteristics by the FBB control. With the layout of a semiconductor integrated circuit disclosed in Patent Document 1, it is difficult to apply a sufficient body bias in portions away from the substrate potential supply cell because of the leak current due to a parasitic bipolar and the well resistance.
Based on the technique disclosed in Patent Document 2, it is possible to expect some reduction in the overall power consumption by dividing the voltage supplied from the power supply circuit and supplying the divided voltages to different stages of semiconductor integrated circuits connected together. In order to increase the number of stages of semiconductor integrated circuits to be connected together, it is necessary to increase the voltage supplied from the power supply circuit. However, increasing the voltage supplied from the power supply circuit by boosting the battery voltage of a battery-powered device, for example, is not practical because the power consumption will be large in other portions. Where the voltage supplied from the power supply circuit is not substantially increased, it is then necessary to lower the operating voltage of the semiconductor integrated circuits. However, it will then be difficult to realize the characteristics improvements by the FBB control.